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| www.fairchildsemi.com TMC2249A Digital Mixer 12 x 12 Bit, 60 MHz Features * * * * * * * * * 60 MHz input and computation rate Two 12-bit multipliers Separate data and coefficient inputs Independent, user-selectable pipeline delays of 1 to 16 clocks on all input ports Separate 16-bit input port allows cascading or addition of a constant User-selectable rounded output Internal 1/2 LSB rounding of products Fully registered, pipelined architecture Available in 120-Pin CPGA, PPGA, MPGA or MQFP Applications * * * * * * Video switching Image mixing Digital signal modulation Complex frequency synthesis Digital filtering Complex arithmetic functions Description The TMC2249A is a high-speed digital arithmetic circuit consisting of two 12-bit multipliers, an adder and a cascadeable accumulator. All four multiplier inputs are simultaneously accessible to the user, and each includes a userprogrammable pipeline delay of up to 16 clocks in length. The 24-bit adder/subtractor is followed by an accumulator and 16-bit input port which allows the user to cascade multiple TMC2249As. A new 16-bit accumulated output is available every clock, up to the maximum rate of 60 MHz. All inputs and outputs are registered except the three-state output enable, and all are TTL compatible. The TMC2249A utilizes a pipelined, bus-oriented structure offering significant flexibility. Input register clock enables and programmable input data pipeline delays on each port offer an adaptable input structure for high-speed digital systems. Following the multipliers, the user may perform addition or subtraction of either product, arithmetic rounding to 16 bits, and accumulation and summation of products with a cascading input. The output port allows access to all 24 bits of the internal accumulator by switching between overlapping least and most-significant 16-bit words, and a three-state output enable simplifies connection to an external system bus. The TMC2249A has numerous applications in digital processing algorithms, from executing simple image mixing and switching, to performing complex arithmetic functions and complex waveform synthesis. FIR filters, digital quadrature mixers and modulators, and vector arithmetic functions may also be implemented with this device. Fabricated in a submicron CMOS process, the TMC2249A operates at guaranteed clock rates of up to 60 MHz over the full temperature and supply voltage ranges. It is pin- and function-compatible with Fairchild's TMC2249, while providing higher speed operation and lower power dissipation. It is available in a 120 pin Ceramic Pin Grid Array (CPGA), 120 pin Plastic Pin Grid Array (PPGA), 120 lead MQFP to PPGA package (MPGA), and a 120 lead Metric Quad FlatPack (MQFP). Logic Symbol TMC2249A Digital Mixer A11-0 ADEL3-0 ENA B11-0 BDEL3-0 ENB C11-0 CDEL3-0 ENC D11-0 DDEL3-0 END CAB15-0 Delay 1-16 Delay 1-16 Delay 1-16 Delay 1-16 RND FT CASEN CLK NEG1 NEG2 SWAP OE ACC S15-0 REV. 1.0.2 7/6/00 PRODUCT SPECIFICATION TMC2249A Block Diagram ADEL3-0 ENA A11-0 BDEL3-0 ENB B11-0 CDEL3-0 ENC C11-0 DDEL3-0 END D11-0 1-16 1-16 1-16 1-16 NEG1 NEG2 RND 2's Comp 2's Comp FT CAS15-0 CASEN 16 I 0 ACC 24 16M 0 1 0 1 16L ACC SWAP OE 16 ENA ADEL3-0 4 A11-0 12 S15-0 12 E 1 12 E 12 12 12 E 16 12 0 1 F 12 x (16:1) MUX 12 2 2 REV. 1.0.2 7/6/00 TMC2249A PRODUCT SPECIFICATION Functional Description The TMC2249A performs the summation of products described by the formula: S(N+5) =A(N-ADEL) x B(N-BDEL) x (-1NEG1(N)) + C(N-CDEL) x D(N-DDEL) x (-1NEG2(N)) + CAS(N+3 x FT) where ADEL through DDEL range from 1 to 16 pipe delays. All inputs and controls utilize pipeline delay registers to maintain synchronicity with the data input during that clock, except when the Cascade data input is routed directly to the accumulator by use of the Feedthrough control. One-half LSB rounding to 16 bits may be performed on the sum of products while summing with the cascade input data. The user may access either the upper or lower 16 bits of the 24-bit accumulator by swapping overlapping registers. The output bus has an asynchronous high-impedance enable, to simplify interfacing to complex systems. Pin Assignments 120 Pin Metric Quad Flat Pack, KE Package Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Name CLK ACC NEG1 NEG2 RND S15 S14 GND S13 S12 S11 VDD S10 S9 S8 GND S7 S8 S5 VDD S4 S3 S2 GND S1 S0 OE SWAP BDEL0 BDEL1 Pin 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Name BDEL2 BDEL3 ENB B0 B1 B2 B3 B4 B5 B6 B7 GND B8 B9 B10 VDD B11 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ENA Pin 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 Name ADEL3 ADEL2 ADEL1 ADEL0 NC CAS15 CAS14 CAS13 CAS12 CAS11 CAS10 GND CAS9 CAS8 CAS7 CAS6 CAS5 CAS4 CAS3 CAS2 CAS1 CAS0 CASEN FT CDEL0 CDEL1 CDEL2 CDEL3 ENC C0 Pin 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Name C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 VDD D11 D10 D9 GND D8 D7 D6 D5 D4 D3 D2 D1 D0 END DDEL3 DDEL2 DDEL1 DDEL0 1 120 91 90 30 31 61 60 REV. 1.0.2 7/6/00 3 PRODUCT SPECIFICATION TMC2249A Pin Assignments 120 Pin Plastic Pin Grid Array, H5 Package, 120 Pin Ceramic Pin Grid Array, G1 Package, and 120 Pin Metric Quad FlatPack to 120 Pin Plastic Pin Array, H6 Package Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 C1 C2 C3 C4 Name DDEL0 DDEL3 END D2 D4 D7 D8 D10 C11 C9 C6 C3 C0 NEG1 ACC DDEL1 D0 D3 D6 D9 D11 C10 C7 C5 C2 CDEL2 S15 RND CLK DDEL2 Pin C5 C6 C7 C8 C9 C10 C11 C12 C13 D1 D2 D3 D11 D12 D13 E1 E2 E3 E11 E12 E13 F1 F2 F3 F11 F12 F13 G1 G2 G3 Name D1 D5 GND VDD C8 C4 C1 ENC CDEL1 S13 S14 GND CDEL3 CDEL0 CASEN S11 S12 GND FT CAS0 CAS1 S9 S10 VDD CAS2 CAS3 CAS4 S7 S8 GND Pin G11 G12 G13 H1 H2 H3 H11 H12 H13 J1 J2 J3 J11 J12 J13 K1 K2 K3 K11 K12 K13 L1 L2 L3 L4 L5 L6 L7 L8 L9 Name CAS6 CAS7 CAS5 S6 S5 VDD GND CAS9 CAS8 S4 S3 GND CAS13 CAS11 CAS10 S2 S1 SWAP ADEL0 CAS14 CAS12 S0 BDEL0 BDEL2 B0 B4 GND VDD A9 A5 Pin L10 L11 L12 L13 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 Name A1 ADEL3 NC CAS15 OE BDEL3 B1 B3 B6 B8 B10 A10 A7 A4 A0 ADEL2 ADEL1 BDEL1 ENB B2 B5 B7 B9 B11 A11 A8 A6 A3 A2 ENA 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L MN KEY Top View Cavity Up 4 REV. 1.0.2 7/6/00 TMC2249A PRODUCT SPECIFICATION Pin Descriptions Pin Number Pin Name CPGA/PPGA/ MQFP MPGA Power VDD GND Clock CLK C3 1 System Clock. The TMC2249A operates from a single master clock input. The rising edge of clock strobes all enabled registers. All timing specifications are referenced to the rising edge of CLK. A-D Input. A through D are the four 12-bit registered data input ports. A0-D0 are the LSBs (see Table 1). Data presented to the input ports is clocked in to the top of the 16-stage delay pipeline on the next clock when enabled, "pushing" data down the register stack. F3, H3, L7, C8 12, 20, 46, 102 Supply Voltage. The TMC2249A operates from a single +5V supply. All power and ground pins must be connected. E3, G3, J3, L6, H11, C7 8, 16, 24, 42, 72, 106 Ground. The TMC2249A operates from a single +5V supply. All power and ground pins must be connected. Pin Function Description Inputs A11-0 N8, M8, L8, 48, 49, 50, 51, N9, M9, N10, 52, 53, 54, 55, L9, M10, N11, 56, 57, 58, 59 N12, L10, M11 N7, M7, N6, M6, N5, M5, N4, L5, M4, N3, M3, L4 47, 45, 44, 43, 41, 40, 39, 38, 37, 36, 35, 34 B11-0 C11-0 A9, B9, A10, 101, 100, 99, C9, B10, A11, 98, 97, 96, 95, B11, C10, A12, 94, 93, 92, 91, B12, C11, A13 90 B8, A8, B7, A7, 103, 104, 105, A6, B6, C6, A5, 107, 108, 109, B5, A4, C5, B4 110, 111, 112 113, 114, 115 L11, M12, M13, K11 D11, B13, C13, D12 61, 62, 63, 64 A-D Delay. ADEL through DDEL are the four-bit registered input data pipe delay select word inputs. Data to be presented to the multipliers is selected from one of sixteen stages in the input data delay pipe registers, as indicated by the delay select word presented to the respective input port during that clock. The minimum delay is one clock (select word=0000), and the maximum delay is 16 clocks (select word=1111). Following powerup these values are indeterminate and must be initialized by the user. Cascade Input. CAS is the 16-bit Cascade data input port. CAS0 is the LSB. See Table 1. D11-0 ADEL3-0 BDEL3-0 CDEL3-0 DDEL3-0 CAS15-0 M2, L3, N1, L2 32, 31, 30, 29 88, 87, 86, 85 A2, C4, B3, A1 117, 118, 119, 120 L13, K12, J11, K13, J12, J13, H12, H13, G12, G11, G13, F13, F12, F11, E13, E12 66, 67, 68, 69, 70, 71, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82 Controls S15-0 C1, D2, D1, 6, 7, 9, 10, 11, E2, E1, F2, F1, 13, 14, 15, 17, G2, G1, H1, 18, 19, 21, 22, H2, J1, J2, K1, 23, 25, 26 K2, L1 Sum Output. The current 16-bit result is available at the Sum output. The output may be the most or least significant 16 bits of the current accumulator output, as determined by SWAP. S0 is the LSB. See Table 1. REV. 1.0.2 7/6/00 5 PRODUCT SPECIFICATION TMC2249A Pin Descriptions (continued) Pin Number Pin Name CPGA/PPGA/ MQFP MPGA Controls ENA-END N13, N2, C12, 60, 33, 89, 116 Input Enables. Input data presented to port i11-0 (i=A,B,C, or D) A3 are latched into delay pipeline i, and data already in pipeline i advance by one register position, on each rising edge of CLK for which ENi is LOW. When ENi is HIGH, the data in pipeline i do not move and the value at the input port i will be lost before it reaches the multiplier. NEG1,2 B1, D3 3, 4 Negate. The products of the multipliers are negated causing a subtraction to be performed during the internal summation of products, when the NEGate controls are HIGH, NEG1 negates the product A x B, while NEG2 acts on the output of the multiplier which generates the product C x D. When the length controls ADEL- DDEL are set to zero, these controls indicate the operation to be performed on data input during the same clock. As nonzero values for ADEL-DDEL do not affect the pipelining of these controls, their effect is not synchronous with the data input in these cases. Round. When the rounding control is HIGH, the 24-bit sum of products resulting from data input during that clock is rounded to 16 bits. When enabled rounding is automatically performed only during the first cycle of each accumulation sequence, to avoid the accumulation of roundoff errors. Feedthrough. When the Feedthrough control is HIGH, the pipeline delay through the cascade data path is minimized to simplify the cascading of multiple devices. When FT is LOW and ADEL through DDEL are all set to 0, the data inputs are aligned, such that S(n+6) = CAS(n) + A(n)B(n) + C(n)D(n). See Table 2. Cascade Enable. Data presented at the cascade data input port are latched and accumulated internally when the input enable CASEN during that clock is LOW. When CASEN is HIGH, the cascade input port is ignored. Accumulate. When the registered ACCumulator control is LOW, no internal accumulation will be performed on the data input during the current clock, effectively clearing the prior accumulated sum. When ACC is HIGH, the internal accumulator adds the emerging product to the sum of the previous products and RND is disabled. Swap Output Words. The user may access both the most and least-significant 16 bits of the 24-bit accumulator by utilizing SWAP. Normal operation of the device, with SWAP = HIGH, outputs the most significant word. Setting SWAP = LOW puts a double-register structure into "toggle" mode, allowing the user to examine the LSW on alternate clocks. New output data will not be clocked into the output registers until SWAP returns HIGH. Output Enable. Data currently in the output registers is available at the output bus S15-0 when the asynchronous Output Enable is LOW. When OE is HIGH, the outputs are in the high-impedance state. Do Not Connect Index Pin (optional) Pin Function Description RND C2 5 FT E11 84 CASEN D13 83 ACC B2 2 SWAP K3 28 OE M1 27 No Connect L12 D4 65 6 REV. 1.0.2 7/6/00 TMC2249A PRODUCT SPECIFICATION Table 1. Data Formats and Bit Weighting 15 -2 23 14 2 22 13 2 21 12 2 20 11 -2 2 11 19 10 2 10 18 9 2 2 9 17 8 2 2 8 16 7 2 2 7 15 6 2 2 6 14 5 2 2 5 13 4 2 2 4 12 3 2 2 3 11 2 2 2 2 10 1 2 1 0 2 0 8 BIT DATA (A11-0-D11-0) CASCADE INPUT (CAS15-0) 2 2 9 2 SUM (S15-0) 2 15 23 2 2 14 22 2 2 13 21 2 12 2 11 19 2 10 2 2 9 2 2 8 2 2 7 2 2 6 2 2 5 2 2 4 2 2 3 2 2 2 2 2 1 9 20 2 8 LSW MSW -2 2 20 2 2 18 17 16 15 14 13 12 11 10 Notes: A minus sign indicates the two's complement sign bit. RND adds 1 to the 27 position if ACC is low. Equivalent Circuits and Threshold Levels VDD VDD p Data or Control Input n p Output n GND GND Figure 1. Equivalent Digital Input Circuit Figure 2. Equivalent Digital Output Circuit tENA OE tDIS 0.5V 2.0V 0.8V High Impedance 0.5V Three-State Outputs Figure 3. Threshold Levels for Three-State Measurement REV. 1.0.2 7/6/00 7 PRODUCT SPECIFICATION TMC2249A Absolute Maximum Ratings (beyond which the device may be damaged)1 Parameter Supply Voltage Input Voltage Applied Voltage (Output) 2 Externally Forced Current (Output) Operating, Ambient Temperature Operating, Junction Temperature Storage Temperature Lead, Soldering (10 seconds) -65 3,4 Min -0.5 -0.5 -0.5 -3.0 -20 Max 7.0 VDD + 0.5 VDD + 0.5 6.0 1 110 140 150 300 Unit V V V mA sec C C C C Output Short Circuit Duration (single output in HIGH state to ground) Notes: 1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if Operating Conditions are not exceeded. 2. Applied voltage must be current limited to specified range. 3. Forcing voltage must be limited to specified range. 4. Current is specified as conventional current flowing into the device. Operating Conditions Parameter VDD fCLK Power Supply Voltage Clock frequency TMC2249A TMC2249A-1 TMC2249A-2 tPWH tPWL tS tH VIH VIL IOH IOL TA CLK pulse width, HIGH CLK pulse width, LOW Input Data Set-up Time Input Data Hold Time Input Voltage, Logic HIGH Input Voltage, Logic LOW Output Current, Logic HIGH Output Current, Logic LOW Ambient Temperature, Still Air 0 Data Inputs CLK Input 6 7 6 1.5 2.0 2.2 0.8 -2.0 4.0 70 Min 4.75 Nom 5.0 Max 5.25 25 40 60 Units V MHz MHz MHz ns ns ns ns V V V mA mA C 8 REV. 1.0.2 7/6/00 TMC2249A PRODUCT SPECIFICATION Electrical Characteristics Parameter IDD Total Power Supply Current Conditions VDD = Max, CLOAD = 25pF, fCLK = Max TMC2249A TMC2249A-1 TMC2249A-2 IDDU Power Supply Current, Unloaded VDD = Max, OE = HIGH, fCLK = Max TMC2249A TMC2249A-1 TMC2249A-2 IDDQ CPIN IIH IIL IOZH IOZL IOS VOH VOL Power Supply Current, Quiescent I/O Pin Capacitance Input Current, HIGH Input Current, LOW Hi-Z Output Leakage Current, Output HIGH Hi-Z Output Leakage Current, Output LOW Short-Circuit Current Output Voltage, HIGH Output Voltage, LOW S15-0, IOH = Max S15-0, IOL = Max VDD = Max, VIN = VDD VDD = Max, VIN = 0 V VDD = Max, VIN = VDD VDD = Max, VIN = 0 V -20 2.4 0.4 VDD = Max, CLK = LOW 5 10 10 10 10 -80 68 92 124 5 mA mA mA mA pF A A A A mA V V 75 105 145 mA mA mA Min Typ Max Units Switching Characteristics Parameter tDO tHO tENA tDIS Output Delay Time Output Hold Time Three-State Output Enable Delay Three-State Output Disable Delay Conditions1 CLOAD = 25 pF CLOAD = 25 pF CLOAD = 0 pF CLOAD = 0 pF 2.5 12 12 Min Typ Max 14 Units ns ns ns ns Note: 1. All transitions are measured at a 1.5V level except for tENA and tDIS. 1/fCLK CLK tS A11-0 D11-0 CONTROLS1 DA 1 2 tH DB 3 tPWH 5 tPWL 6 7 tDO S15-0 2 tHO SA 1Except OE. 2Assumes OE = LOW and ADEL-DDEL set to 0. Figure 4. Timing Diagram REV. 1.0.2 7/6/00 9 PRODUCT SPECIFICATION TMC2249A Application Notes The TMC2249A is a flexible signal and image processing building block with numerous user-selectable functions which expand its usefulness. Table 2 clarifies the operation of the device, demonstrating the various feature available to the user and the timing delays incurred. Table 2. TMC2249A Operation Sequence CLK ADEL A11-0 BDEL B11-0 CDEL C11-0 DDEL D11-0 NEG1 NEG2 CAS15-0 FT 1 0 A(1) 0 B(1) 0 C(1) 0 D(1) L L 0 L 2 3 4 5 6 7 8 9 10 11 12 13 14 0 0 0 0 0 0 0 0 A(2) A(3) A(4) A(5) A(6) A(7) A(8) A(9) 0 0 0 0 0 0 0 0 B(2) B(3) B(4) B(5) B(6) B(7) B(8) B(9) 0 0 0 0 0 0 0 0 C(2) C(3) C(4) C(5) C(6) C(7) C(8) C(9) 0 0 0 0 0 0 0 0 D(2) D(3) D(4) D(5) D(6) D(7) D(8) D(9) L H L L L L L L H L L L L L L L 0 0 CAS(4) 0 0 0 CAS(8) 0 L L L L L L H L ACC RND SWAP L L L L L L H L L H H L L L H X L H H H H H H H H L H S15-0 -- -- -- -- -- (A(1) x B(1)+C(1) x D(1)+27)ms (A(2) x B(2)-C(2) x D(2)+27)ms (-A(3) x B(3)+C(3) x D(3))ms (A(4) x B(4)+C(4) x D(4)+CAS(4))ms (A(5) x B(5)+C(5) x D(5)+CAS(8))ms (A(6) x B(6)+C(6) x D(6)+27)ms (A(7) x B(7)+C(7) x D(7)+S(11))ms (S(12))ls (A(9) x B(8)+C(7) x D(6)+27)ms CASEN = 0, H=HIGH, L=LOW, "ms" indicates most significant output word (bits 23-8), "ls" indicates least significant word (bits 15-0). The appropriate enables for the indicated data are assumed, otherwise `-' indicates that port not enabled. Note that the output data summations including A(8)-D(8) is lost, since the output on cycle 13 is swapped to the LSW of S(12) on cycle 8. In general, RND may be left high unless the ls output is to be used, as on line 8 above. Digital Filtering The input structure of the TMC2249A demonstrates great versatility when all four multiplier inputs and the programmable delay registers are utilized. Table 3 and Table 4 illlustrate how a direct-form symmetric FIR filter of up to 32 taps can be implemented. By utilizing the four input delay registers as pipelined storage banks, the user can store up to 32 coefficient-data word pairs, split into alternate "even" and "odd" halves. Two taps of the filter are calculated on each clock, and the user then increments/decrements the delay words (ADEL-DDEL). The sums of products are successively added to the global sum in the internal accumulator. Table 3. FIR Filtering with the TMC2249A--Initial Data Loading Register Position (Hex) 0 1 2 3 4 5 6 7 8 9 A B C D E F 10 Even Data A x(31) x(29) x(27) x(25) x(23) x(21) x(19) x(17) x(15) x(13) x(11) x(9) x(7) x(5) x(3) x(1) Odd Data C x(30) x(28) x(26) x(24) x(22) x(20) x(18) x(16) x(14) x(12) x(10) x(8) x(6) x(4) x(2) x(0) Coefficient B h(0) h(2) h(4) h(6) h(8) h(10) h(12) h(14) h(15) h(13) h(11) h(9) h(7) h(5) h(3) h(1) Storage D h(1) h(3) h(5) h(7) h(9) h(11) h(13) h(15) h(14) h(12) h(10) h(8) h(6) h(4) h(2) h(0) REV. 1.0.2 7/6/00 TMC2249A PRODUCT SPECIFICATION Once all of the products of the desired taps have been summed, the result is available at the output. The user then "pushes" a new time-data sample on to the appropriate even or odd data register "stack" and reiterates the summation. Note that the coefficient bank "pointers", the BDEL and DDEL delay words, are alternately incremented and decremented on successive filter passes to maintain alignment between the incoming data samples and their respective coefficients. The effective filter speed is calculated by dividing the clock rate by one-half the number of taps implemented. Alternatively, non-symmetric FIR filters can be implemented using the TMC2249A in a similar fashion. Here, a shift register is used to delay the incoming data fed to the A input by an amount equal to one-half the length of the filter (the length of the A delay register). As shown in Figure 5, the data is then sent to the C input, thus "stacking" the A and C delay registers to create a single N-tap FIR filter. The incremented delay words (ADELDDEL) for all four inputs are identical. Again, the filter throughput is equal to the clock speed divided by one-half the number of taps implemented. TMC2011A 16-Stage Shift Register A x(m+0) x(m+15) B h(0) h(15) S15-0 Filter Output C x(m+16) x(m+31) D h(16) h(31) x(m) TMC2249A Figure 5. Non-Symmetric 32-Tap FIR Filtering Using the TMC2249A Table 4. FIR Filtering - Operation Sequence Cycle 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 * * Push A - - - - - - - - - - - - - - - - - - - - - B - - - - - - - - - - - - - - - - - - - - - Push C - - - - - - - - - - - - - - - x(32) - - - - - D - - - - - - - - - - - - - - - - - - - - - ADEL 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 CDEL 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 BDEL 0 1 2 3 4 5 6 7 8 9 A B C D E F F E D C B DDEL 0 1 2 3 4 5 6 7 8 9 A B C D E F F E D C B ACC L H H H H H H H H H H H H H H H H H H H H ENA H H H H H H H H H H H H H H H H H H H H H ENB H H H H H H H H H H H H H H H H H H H H H ENC H H H H H H H H H H H H H H H L H H H H H END H H H H H H H H H H H H H H H H H H H H H Convolutional Sum x(31)*h(0)+x(30)*h(1) +x(29)*h(2)+x(28)*h(3) +x(27)*h(4)+x(26)*h(5) +x(25)*h(6)+x(24)*h(7) +x(23)*h(8)+x(22)*h(9) +x(21)*h(10)+x(20)*h(11) +x(19)*h(12)+x(18)*h(13) +x(17)*h(14)+x(16)*h(15) +x(15)*h(15)+x(14)*h(14) +x(13)*h(13)+x(12)*h(12) +x(11)*h(11)+x(10)*h(10) +x(9)*h(9)+x(8)*h(8) +x(7)*h(7)+x(6)*h(6) +x(5)*h(5)+x(4)*h(4) +x(3)*h(3)+x(2)*h(2) +x(1)*h(1)+x(0)*h(0) +x(31)*h(1)+x(32)*h(0) +x(29)*h(3)+x(30)*h(2) +x(27)*h(5)+x(28)*h(4) +x(25)*h(7)+x(26)*h(6) +x(23)*h(9)+x(24)*h(8) Resultant Output See Note 2 Notes: 1. If only the 16 MSBs of the result are used, the user may leave RND HIGH and SWAP low. If the 16 LSBs or all 24 bits of the result are used, then RND should be set low. 2. s= K=0 15 ( x ( k )h ( k ) + x ( k + 16 )h ( k ) ) REV. 1.0.2 7/6/00 11 PRODUCT SPECIFICATION TMC2249A Complex Arithmetic Functions The TMC2249A can also be used to perform complex arithmetic functions. The basic function performed by the device, ignoring the delay controls, SUM = (A*B) + (C*D) can realize in two steps the familiar summation: (P+jR)(S+jT)=(PS-RT) + j(PT+SR) (1) (2) Expanding the complex vectors A and B to calculate X and Y, we get: X = (Re(A)+jlm(A))+(Re(B)Re(W)lm(B)lm(W)+j(Re(B)lm(W)+lm(B)Re(W))) = (Re(A)+Re(B)Re(W)lm(B)lm(W))+j(lm(A)+Re(B)lm(W)+lm(B)Re(W)) = and, Y = (Re(A)+jlm(A))-(Re(B)Re(W)lm(B)lm(W)+j(Re(B)lm(W)+lm(B)Re(W))) Re(X)+jlm(X) by loading the TMC2249A as follows: TMC2249A Inputs Step 1 2 A P P B S T C R R D T S NEG1 NEG2 L L H L Resultant Output (PS-RT) (PT+SR) = (Re(A)Re(B)Re(W)+lm(B)lm(W))+j(lm(A)-Re(B)lm(W)lm(B)Re(W)) = Re(Y)+jlm(Y) where H and L indicate a logic HIGH and LOW. Thus we can perform a complex multiplication in two clock cycles. Notice that the user must switch the two components of the second input vector between the B and D inputs to obtain the second complex summation. The butterfly is then neatly implemented in four clocks, as follows: TMC2249A Inputs Step 1 2 3 4 A B C D CAS Input NEG1 L H L H Resultant NEG2 Output H L L H Re(X) Re(Y) Im(X) Im(Y) Calculating a Butterfly Taking advantage of the complex multiply which we implemented above using the TMC2249A, we can expand slightly to calculate a Radix-2 Butterfly, the core of the Fast Fourier Transform algorithm. To review, the Butterfly is calculated as shown in Figure 6. A X Re(B) Re(W) Im(B) Im(W) Re(A) Re(B) Re(W) Im(B) Im(W) Re(A) Re(B) Im(W) Im(B) Re(W) Im(A) Re(B) Im(W) Im(B) Re(W) Im(A) Notice again that the components of the second vector must be switched by the user on the second half of the computation, as well as the parts of the vector presented to the cascade input. WNr B -1 Y Quadrature Modulation The TMC2249A can also be used to advantage as a digitaldomain complex frequency synthesizer, as demonstrated in Figure 7. Here, orthogonal sinusoidal waveforms are generated digitally in the TMC2330A Coordinate Transformer. These quadrature phase coefficients are then multiplied with two input signals, such as digitized analog data. The TMC2249A then adds these products, which can be output directly to a high-speed digital-to-analog converter such as the Fairchild TDC1012 for direct waveform synthesis. This 12-bit, 20MHz DAC is ideally suited to waveform generation, featuring extremely low glitch energy for low spurious harmonics and distortion. Figure 6. Signal Flow of Radix-2 Butterfly Where X=A+B(WNr) Y=A-B(WNr), and WNr is the complex phase coefficient, or "twiddle factor" for the N-point transform, which is: WNr = = = ej(2/N) cos(2/N) + j(sin(2/N)) Re(W) + jIm(W) with Re and Im indicating the real and imaginary parts of the vector. 12 REV. 1.0.2 7/6/00 TMC2249A PRODUCT SPECIFICATION 0 1 I = Signal 1 1 RTP A = Mixer Amplitude XRIN TCXY RXOUT(15:4) A B[11:0] SWAP S15-0 TMC2249A Output = A * (I*cos(wt) +Q*sin(wt)) TMC2330A F = Mixer Frequency YPIN PYOUT(15:4) ACC C[11:0] D ENA-D 4 01 Q = Signal 2 0 Figure 7. Direct Quadrature Waveform Synthesizer using the TMC2249A and TMC2330A Related Products * * * * TMC2301 Image Resampling Sequencer TMC2302A Image Manipulation Sequencer TMC2246A Image Filter TMC2242B Half-Band Filter REV. 1.0.2 7/6/00 13 TMC2249A PRODUCT SPECIFICATION Mechanical Dimensions 120-Lead CPGA Package Symbol A A1 A2 oB oB2 D D1 e L L1 M N P Inches Min. Max. Millimeters Min. Max. Notes: Notes 1. Pin #1 identifier shall be within shaded area shown. 2. Pin diameter excludes solder dip finish. 3. Dimension "M" defines matrix size. 4. Dimension "N" defines the maximum possible number of pins. 2 2 SQ 5. Orientation pin is at supplier's option. 6. Controlling dimension: inch. .080 .160 .040 .060 .125 .215 .016 .020 .050 NOM. 1.340 1.380 1.200 BSC .100 BSC .110 .145 .170 .190 13 120 .003 -- 2.03 4.06 1.01 1.53 3.17 5.46 0.40 0.51 1.27 NOM. 33.27 35.05 30.48 BSC 2.54 BSC 2.79 3.68 4.31 4.83 13 120 .076 -- 3 4 A2 A1 L D e oB oB2 P A Top View Cavity Up D1 Pin 1 Identifier REV. 1.0.2 7/6/00 14 TMC2249A PRODUCT SPECIFICATION Mechanical Dimensions 120-Lead PPGA Package Inches Min. A A1 A2 oB oB2 D D1 e L L1 M N P Max. Millimeters Min. Max. Notes: Notes 1. Pin #1 identifier shall be within shaded area shown. 2. Pin diameter excludes solder dip finish. 3. Dimension "M" defines matrix size. 4. Dimension "N" defines the maximum possible number of pins. 2 2 SQ 5. Orientation pin is at supplier's option. 6. Controlling dimension: inch. Symbol .080 .160 .040 .060 .125 .215 .016 .020 .050 NOM. 1.340 1.380 1.200 BSC .100 BSC .110 .145 .170 .190 13 120 .003 -- 2.03 4.06 1.01 1.53 3.17 5.46 0.40 0.51 1.27 NOM. 33.27 35.05 30.48 BSC 2.54 BSC 2.79 3.68 4.31 4.83 13 120 .076 -- 3 4 A2 A1 L D e oB oB2 P A Top View Cavity Up D1 Pin 1 Identifier REV. 1.0.2 7/6/00 15 PRODUCT SPECIFICATION TMC2249A Mechanical Dimensions 120-Lead Metric Quad Flat Package to Pin Grid Array Package (MPGA) Symbol A A1 A2 A3 oB oB2 D D1 e L M N Inches Min. Max. Millimeters Min. Max. Notes: Notes 1. Pin #1 identifier shall be within shaded area shown. 2. Pin diameter excludes solder dip finish. 3. Dimension "M" defines matrix size. 4. Dimension "N" defines the maximum possible number of pins. 5. Orientation pin is at supplier's option. 2 2 SQ 6. Controlling dimension: inch. .309 .311 .145 .155 .080 .090 .050 TYP. .016 .020 .050 NOM. 1.355 1.365 1.200 BSC .100 BSC .175 .185 13 120 7.85 7.90 3.68 3.94 2.03 2.29 1.27 TYP. 0.40 0.51 1.27 NOM. 34.42 34.67 30.48 BSC 2.54 BSC 4.45 4.70 13 120 3 4 A A1 L A3 oB2 oB e A2 D e Fairchild TMC2249A D1 Pin 1 Identifier 16 REV. 1.0.2 7/6/00 TMC2249A PRODUCT SPECIFICATION Mechanical Dimensions 120-Lead MQFP Package Inches Min. A A1 A2 B C D/E D1/E1 e L N ND ccc Symbol Millimeters Min. Max. Notes: Notes 1. All dimensions and tolerances conform to ANSI Y14.5M-1982. 2. Controlling dimension is millimeters. 3. Dimension "B" does not include dambar protrusion. Allowable dambar protrusion shall be .08mm (.003in.) maximum in excess of the "B" dimension. Dambar cannot be located on the lower radius or the foot. 4. "L" is the length of terminal for soldering to a substrate. 5. "B" & "C" includes lead finish thickness. Max. -- .154 .010 -- .125 .144 .018 .012 .009 .005 1.219 1.238 1.098 1.106 .0315 BSC .026 .037 120 30 0 -- 7 .004 -- 3.92 .25 -- 3.17 3.67 .45 .30 .23 .13 30.95 31.45 27.90 28.10 .80 BSC .65 .95 120 30 0 -- 7 .10 3, 5 5 4 .20 (.008) Min. D D1 e PIN 1 IDENTIFIER E 0.063" Ref (1.60mm) Lead Detail E1 0 Min. .13 (.005) R Min. .13/.30 R .005/.012 C L See Lead Detail A A2 B A1 Seating Plane Base Plane -CLEAD COPLANARITY ccc C REV. 1.0.2 7/6/00 17 PRODUCT SPECIFICATION TMC2249A Ordering Information Product Number TMC2249AG1C TMC2249AG1C1 TMC2249AG1C2 TMC2249AH5C TMC2249AH5C1 TMC2249AH5C2 TMC2249AH6C TMC2249AH6C1 TMC2249AH6C2 TMC2249AKEC TMC2249AKEC1 TMC2249AKEC2 Temperature Range 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C Speed Grade 25 MHz 40 MHz 60 MHz 25 MHz 40 MHz 60 MHz 25 MHz 40 MHz 60 MHz 25 MHz 40 MHz 60 MHz Screening Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Package 120 Pin Ceramic Pin Grid Array 120 Pin Ceramic Pin Grid Array 120 Pin Ceramic Pin Grid Array 120 Pin Plastic Pin Grid Array 120 Pin Plastic Pin Grid Array 120 Pin Plastic Pin Grid Array 120 Lead Metric Quad Flat Pack to Pin Grid Array 120 Lead Metric Quad Flat Pack to Pin Grid Array 120 Lead Metric Quad Flat Pack to Pin Grid Array 120 Lead Metric Quad Flat Pack 120 Lead Metric Quad Flat Pack 120 Lead Metric Quad Flat Pack Package Marking 2249AG1C 2249AG1C1 2249AG1C2 2249AH5C 2249AH5C1 2249AH5C2 N/A N/A N/A 2249AKEC 2249AKEC1 2249AKEC2 LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 7/6/00 0.0m 002 Stock#DS30002249A 2000 Fairchild Semiconductor Corporation |
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